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4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7193
FEATURES
Fast settling filter option 4 differential/8 pseudo differential input channels RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: 5 nV/C Gain drift: 1 ppm/C Specified drift over time Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply AVDD: 3 V to 5.25 V DVDD: 2.7 V to 5.25 V Current: 4.65 mA Temperature range: -40C to +105C Package: 28-lead TSSOP Interface 3-wire serial SPI, QSPITM, MICROWIRETM, and DSP compatible Schmitt trigger on SCLK Temperature measurement Flow measurement Weigh scales Chromatography Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7193 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (-) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC. The device can be configured to have four differential inputs or eight pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled simultaneously, and the AD7193 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz. The device has a very flexible digital filter, including a fast settling option. Variables such as output data rate and settling time are dependent on the option selected. For applications that require all conversions to be settled, the AD7193 includes zero latency. The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.65 mA and it is housed in a 28-lead TSSOP package.
APPLICATIONS
PLC/DCS analog input modules Data acquisition Strain gage transducers Pressure measurement
AVDD AGND DVDD DGND
FUNCTIONAL BLOCK DIAGRAM
REFIN1(+) REFIN1(-)
AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AINCOM
AD7193
DOUT/RDY DIN SCLK CS SYNC TEMP SENSOR P3 P2 CLOCK CIRCUITRY
08367-001
MUX
PGA
- ADC
SERIAL INTERFACE AND CONTROL LOGIC
BPDSW
AGND MCLK1 MCLK2 P0/REFIN2(-) P1/REFIN2(+)
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
AD7193 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 RMS Noise and Resolution............................................................ 15 Sinc Chop Disabled ................................................................... 15 Sinc Chop Disabled ................................................................... 16 Fast Settling ................................................................................. 17 On-Chip Registers .......................................................................... 18 Communications Register ......................................................... 19 Status Register ............................................................................. 20 Mode Register ............................................................................. 21 Configuration Register .............................................................. 24 Data Register ............................................................................... 26 ID Register ................................................................................... 26 GPOCON Register ..................................................................... 26 Offset Register ............................................................................. 27 Full-Scale Register ...................................................................... 27 ADC Circuit Information .............................................................. 28 Overview...................................................................................... 28 Analog Input Channel ............................................................... 29 Programmable Gain Array (PGA) ........................................... 29
3 4
Reference ..................................................................................... 29 Reference Detect ......................................................................... 30 Bipolar/Unipolar Configuration .............................................. 30 Data Output Coding .................................................................. 30 Burnout Currents ....................................................................... 30 Channel Sequencer .................................................................... 30 Digital Interface .......................................................................... 31 Reset ............................................................................................. 35 System Synchronization ............................................................ 35 Enable Parity ............................................................................... 35 Clock ............................................................................................ 35 Bridge Power-Down Switch ...................................................... 35 Temperature Sensor ................................................................... 36 Logic Outputs ............................................................................. 36 Calibration................................................................................... 36 Digital Filter .................................................................................... 38 Sinc4 Filter (Chop Disabled) ..................................................... 38 Sinc3 Filter (Chop Disabled) ..................................................... 40 Chop Enabled (Sinc4 Filter) ...................................................... 42 Chop Enabled (Sinc3 Filter) ...................................................... 44 Fast Settling Mode (Sinc4 Filter) ............................................... 45 Fast Settling Mode (Sinc3 Filter) ............................................... 47 Fast Settling Mode (Chop Enabled) ......................................... 49 Summary of Filter Options ....................................................... 50 Grounding and Layout .................................................................. 51 Applications Information .............................................................. 52 Flowmeter.................................................................................... 52 Outline Dimensions ....................................................................... 53 Ordering Guide .......................................................................... 53
REVISION HISTORY
9/09--Rev. 0 to Rev. A Changes to Internal/External Clock, Internal Clock Frequency Parameter, Table 1............................................................................. 5 Changes to Figure 6 and Figure 7 ................................................. 12 Changes to Table 6 .......................................................................... 15 Changes to Table 9 .......................................................................... 16 Changes to Table 12, Table 13, and Table 14 ............................... 17 Changes to Table 19 ........................................................................ 22 Changes to Table 22 and Table 23 ................................................ 25 Changes to Offset Register and Full-Scale Register Sections ... 27 Changes to Reference Section ....................................................... 29 Changes to Data Output Coding Section .................................... 30 Changes to Sinc4 50 Hz/60 Hz Rejection Section ...................... 39 Changes to Sinc3 50 Hz/60 Hz Rejection Section ...................... 41 Changes to 50 Hz/60 Hz Rejection, Sinc4 Filter Section ........... 45 Changes to Summary of Filter Options Section and Table 35.. 50 7/09--Revision 0: Initial Version
Rev. A | Page 2 of 56
AD7193 SPECIFICATIONS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AVDD, REFINx(-) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter ADC Output Data Rate Min 4.7 1.17 1.56 24 24 Typ Max 4800 1200 1600 Unit Hz Hz Hz Bits Bits Test Conditions/Comments 1 Chop disabled Chop enabled, sinc4 filter Chop enabled, sinc3 filter FS[9:0] 3 > 1, sinc4 filter FS[9:0]3 > 4, sinc3 filter See the RMS Noise and Resolution section See the RMS Noise and Resolution section
No Missing Codes 2 Resolution RMS Noise and Output Data Rates Integral Nonlinearity Gain = 12 Gain > 1 Offset Error 4 , 5
Offset Error Drift vs. Temperature
2 2 5 15 150/gain 1 0.5 150/gain 5 5 25 0.001 -0.39 0.003 0.005
10 15 30 30
ppm of FSR ppm of FSR ppm of FSR ppm of FSR V V V nV/C nV/C nV/C nV/1000 hours % % % % ppm/C ppm/1000 hours dB dB dB dB dB dB dB dB dB
AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V Chop disabled Chop enabled, AVDD = 5 V Chop enabled, AVDD = 3 V Gain = 1 to 16; chop disabled Gain = 32 to 128; chop disabled Chop enabled Gain > 32 AVDD = 5 V, gain = 1, TA = 25C (factory calibration conditions) Gain = 128, before full-scale calibration (see Table 26) Gain > 1, after internal full-scale calibration, AVDD 4.75 V Gain > 1, after internal full-scale calibration, AVDD < 4.75 V
Offset Error Drift vs. Time Gain Error4
Gain Drift vs. Temperature Gain Drift vs. Time Power Supply Rejection 95 Common-Mode Rejection @ DC @ DC @ 50 Hz, 60 Hz2 @ 50 Hz2 @ 60 Hz2 @ 50 Hz2 @ 60 Hz2
1 10 90 110 110 105 120 120 120 115 115
Gain = 1 Gain = 1, VIN = 1 V Gain > 1, VIN = 1 V/gain Gain = 1, VIN = 1 V Gain > 1, VIN = 1 V/gain 10 Hz output data rate, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, 50 Hz 1 Hz 60 Hz output data rate, 60 Hz 1 Hz Fast settling, FS[9:0]3 = 6, average by 16, 50 Hz 1 Hz Fast settling, FS[9:0]3 = 5, average by 16, 60 Hz 1 Hz
Rev. A | Page 3 of 56
AD7193
Parameter Normal-Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz Min Typ Max Unit Test Conditions/Comments 1
100 74
dB dB dB dB dB dB dB dB
@ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz
96 97 120 82
10 Hz output data rate, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, REJ60 6 = 1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, 50 Hz 1 Hz 60 Hz output data rate, 60 Hz 1 Hz 10 Hz output data rate, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, REJ606 = 1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, 50 Hz 1 Hz 60 Hz output data rate, 60 Hz 1 Hz
@ 50 Hz @ 60 Hz Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz
120 120
75 60
dB dB dB dB dB dB dB dB
@ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 50 Hz @ 60 Hz Fast Settling Internal Clock @ 50 Hz @ 60 Hz External Clock @ 50 Hz @ 60 Hz ANALOG INPUTS Differential Input Voltage Ranges
70 70 100 67 95 95
10 Hz output data rate, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, REJ606 = 1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, 50 Hz 1 Hz 60 Hz output data rate, 60 Hz 1 Hz 10 Hz output data rate, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, REJ606 = 1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 Hz output data rate, 50 Hz 1 Hz 60 Hz output data rate, 60 Hz 1 Hz
26 26 40 40 VREF/gain -(AVDD - 1.25 V)/gain +(AVDD - 1.25 V)/gain
dB dB dB dB V V
FS[9:0]3 = 6, average by 16, 50 Hz 0.5 Hz FS[9:0]3 = 5, average by 16, 60 Hz 0.5 Hz FS[9:0]3 = 6, average by 16, 50 Hz 0.5 Hz FS[9:0]3 = 5, average by 16, 60 Hz 0.5 Hz VREF = REFINx(+) - REFINx(-), gain = 1 to 128 Gain > 1
Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode Analog Input Current Buffered Mode Input Current2 Input Current Drift Unbuffered Mode Input Current
AGND - 0.05 AGND + 0.25
AVDD + 0.05 AVDD - 0.25
V V
-2 -3 5 3.5 1 0.05 1.6
+2 +3
nA nA pA/C A/V A/V nA/V/C nA/V/C
Gain = 1 Gain > 1
Input Current Drift
Gain = 1, input current varies with input voltage Gain > 1 External clock Internal clock
Rev. A | Page 4 of 56
AD7193
Parameter REFERENCE INPUT REFIN Voltage Min 1 Typ Max AVDD Unit V Test Conditions/Comments1 REFIN = REFINx(+) - REFINx(-), the differential input must be limited to (AVDD - 1.25 V)/gain when gain > 1
Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH RON Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (P0 to P3) Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current2 Floating-State Output Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Crystal Frequency Input Low Voltage, VINL Input High Voltage, VINH Input Current LOGIC INPUTS Input High Voltage, VINH2 Input Low Voltage, VINL2 Hysteresis2 Input Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 Output Low Voltage, VOL2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding
AGND - 0.05 4.5 0.03 1.3 Same as for analog inputs 100 0.3 2 2815
AVDD + 0.05
V A/V nA/V/C nA/V/C External clock Internal clock
dB 0.6 V C Codes/C Applies after user calibration at 25C Bipolar mode
10 30 500
mA nA
Continuous current Analog inputs must be buffered and chop disabled AVDD = 3 V, ISOURCE = 100 A AVDD = 5 V, ISOURCE = 200 A AVDD = 3 V, ISINK = 100 A AVDD = 5 V, ISINK = 800 A
AVDD - 0.6 4 0.4 0.4 +100 10
-100
V V V V nA pF
4.72
4.92 50:50 4.9152
5.12
MHz % MHz V V V V A V V V A V V V V A pF DVDD = 3 V, ISOURCE = 100 A DVDD = 5 V, ISOURCE = 200 A DVDD = 3 V, ISINK = 100 A DVDD = 5 V, ISINK = 1.6 mA
2.4576
5.12 0.8 0.4
2.5 3.5 -10 2 0.1 -10 DVDD - 0.6 4
DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 5 V
+10
0.8 0.25 +10
-10 10 Offset binary
0.4 0.4 +10
Rev. A | Page 5 of 56
AD7193
Parameter SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS7 Power Supply Voltage AVDD - AGND DVDD - DGND Power Supply Currents AIDD Current Min Typ Max 1.05 x FS -1.05 x FS 0.8 x FS 2.1 x FS Unit V V V Test Conditions/Comments1
3 2.7 0.85 1 2.8 3.2 3.8 4.3 0.35 0.5 1.5
5.25 5.25 1 1.25 3.6 3.9 4.7 5.3 0.4 0.6 3
V V mA mA mA mA mA mA mA mA mA A Gain = 1, buffer off Gain = 1, buffer on Gain = 8, buffer off Gain = 8, buffer on Gain = 16 to 128, buffer off Gain = 16 to 128, buffer on DVDD = 3 V DVDD = 5 V External crystal used Power-down mode
DIDD Current
IDD
1 2
Temperature range: -40C to +105C. Specification is not production tested but is supported by characterization data at initial product release. 3 FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system fullscale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND.
Rev. A | Page 6 of 56
AD7193
TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
Parameter READ AND WRITE OPERATIONS t3 t4 READ OPERATION t1 Limit at TMIN, TMAX (B Version) 100 100 0 60 80 0 60 80 10 80 0 10 0 30 25 0 Unit ns min ns min ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min ns min ns min ns min ns min Conditions/Comments 1, 2 SCLK high pulse width SCLK low pulse width CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time
t2 3
t5 5, 6 t6 t7 WRITE OPERATION t8 t9 t10 t11
1 2
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.
Circuit and Timing Diagrams
ISINK (1.6mA WITH DVDD = 5V, 100A WITH DVDD = 3V) TO OUTPUT PIN 50pF ISOURCE (200A WITH DVDD = 5V, 100A WITH DVDD = 3V)
08367-002
1.6V
Figure 2. Load Circuit for Timing Characterization
Rev. A | Page 7 of 56
AD7193
CS (I)
t1
DOUT/RDY (O) MSB LSB
t6 t5
t2 t3
SCLK (I)
t7
t4
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I)
t8
SCLK (I)
t11
t9 t10
DIN (I) MSB I = INPUT, O = OUTPUT LSB
08367-004
Figure 4. Write Cycle Timing Diagram
Rev. A | Page 8 of 56
08367-003
AD7193 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter AVDD to AGND DVDD to AGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AINx/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow Rating -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to +0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to DVDD + 0.3 V 10 mA -40C to +105C -65C to +150C 150C 260C
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Package Type 28-Lead TSSOP JA 97.9 JC 14 Unit C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. A | Page 9 of 56
AD7193 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
MCLK1 1 MCLK2 2 SCLK 3 CS 4 P3 5 P2 6 P1/REFIN2(+) 7 P0/REFIN2(-)
8 28 27 26 25 24
DIN DOUT/RDY SYNC DVDD AVDD DGND AGND BPDSW REFIN1(-) REFIN1(+) AIN8 AIN7 AIN6
08367-005
AD7193
TOP VIEW (Not to Scale)
23 22 21 20 19 18 17 16 15
NC 9 AINCOM 10 AIN1 11 AIN2 12 AIN3 13 AIN4 14
AIN5
NC = NO CONNECT
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 Mnemonic MCLK1 MCLK2 Description When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(-). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN2(+) - REFIN2(-)), is AVDD, but the part functions with a reference from 1 V to AVDD. Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(-). This reference input can lie anywhere between AGND and AVDD - 1 V. No Connect. Tie this pin to AGND. Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential operation. Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM.
3
SCLK
4
CS
5 6 7
P3 P2 P1/REFIN2(+)
8
P0/REFIN2(-)
9 10 11 12 13 14
NC AINCOM AIN1 AIN2 AIN3 AIN4
Rev. A | Page 10 of 56
AD7193
Pin No. 15 16 17 18 19 Mnemonic AIN5 AIN6 AIN7 AIN8 REFIN1(+) Description Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN6 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN5 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN8 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN7 or as a pseudo differential input when used with AINCOM. Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(-). REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) - REFIN1(-)), is AVDD, but the part functions with a reference from 1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between AGND and AVDD - 1 V. Bridge Power-Down Switch to AGND. Analog Ground Reference Point. Digital Ground Reference Point. Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DVDD at 5 V or vice versa. Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7193 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register.
20 21 22 23 24 25 26
REFIN1(-) BPDSW AGND DGND AVDD DVDD SYNC
27
DOUT/RDY
28
DIN
Rev. A | Page 11 of 56
AD7193 TYPICAL PERFORMANCE CHARACTERISTICS
8,387,486 8,387,484 8,387,482 8,387,480
OCCURRENCE CODE
50
40
8,387,478 8,387,476 8,387,474 8,387,472 8,387,470
08367-006
30
20
10
8,387,468
SAMPLE
CODE
Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)
200
Figure 9. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter)
8,388,880 8,388,878
150
8,388,876 8,388,874
CODE
OCCURRENCE
100
8,388,872 8,388,870
50
8,388,868 8,388,866
08367-010
0
08367-007
8,388,864
8,387,470 8,387,474 8,387,478 8,387,482 8,387,472 8,387,476 8,387,480 8,387,484
0
200
400 SAMPLE
600
800
1000
CODE
Figure 7. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)
8,388,920 8,388,910 8,388,900 8,388,890 CODE 8,388,880 8,388,870 8,388,860 8,388,850 8,388,840
08367-008
Figure 10. Noise (VREF = AVDD = 5 V, Output Data Rate = 42.1 Hz (FS[9:0] = 6, Average by 16), Gain = 1, Chop Disabled, Sinc4 Filter)
200
150
OCCURRENCE
100
50
0
200
400 SAMPLE
600
800
1000
CODE
Figure 8. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter)
Figure 11. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 42.1 Hz (FS[9:0] = 6, Average by 16), Gain = 1, Chop Disabled, Sinc4 Filter)
Rev. A | Page 12 of 56
08367-011
8,388,830
0 8,388,864
8,388,868
8,388,872
8,388,876
8,388,880
08367-009
0
200
400
600
800
1000
0 8,388,830
8,388,860
8,388,890
8,388,920
AD7193
5 4 3
INL (ppm of FSR)
0.4 0.2 0 -0.2
2 1 0
OFFSET (V)
-0.4 -0.6 -0.8 -1.0
-1 -2 -4
-1.2
08367-015
-3
-2
-1
0 VIN (V)
1
2
3
4
08367-012
-1.4 -60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 12. INL (Gain = 1)
20 15 10
Figure 15. Offset vs. Temperature (Gain = 128, Chop Disabled)
1.000008 1.000006 1.000004 1.000002
INL (ppm of FSR)
5
GAIN
1.000000 0.999998 0.999996 0.999994
0 -5 -10
0.999992
-15 -20 -0.03
0.999990
08367-013
-0.02
-0.01
0 VIN (V)
0.01
0.02
0.03
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 13. INL (Gain = 128)
170 168 166
OFFSET (V)
Figure 16. Gain vs. Temperature (Gain = 1)
128.004 128.002 128.000 127.998
164 162 160 158 156 154 -60
GAIN
127.996 127.994 127.992 127.990
08367-014
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 14. Offset vs. Temperature (Gain = 1, Chop Disabled)
Figure 17. Gain vs. Temperature (Gain = 128)
Rev. A | Page 13 of 56
08367-017
127.988 -60
08367-016
0.999988 -60
AD7193
24 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128
23 22 NOISE FREE RESOLUTION (Bits) 21 20 19 18 17
08367-022
NOISE FREE RESOLUTION (Bits)
22
GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128
20
18
16
08367-018
14
1
10
100 OUTPUT DATA RATE (Hz)
1k
10k
16
1
10
100
1k
OUTPUT DATA RATE (Hz)
Figure 18. Noise Free Resolution (Sinc4 Filter, Chop Disabled, VREF = 5 V)
24 22
NOISE FREE RESOLUTION (Bits)
Figure 20. Noise Free Resolution in Fast Settling Mode (VREF = 5 V, Averaging by 16, Sinc4 Filter, Chop Disabled)
20 18 16 14 12 10
GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128
1
10
100 OUTPUT DATA RATE (Hz)
1k
10k
Figure 19. Noise Free Resolution (Sinc3 Filter, Chop Disabled, VREF = 5 V)
08367-019
Rev. A | Page 14 of 56
AD7193 RMS NOISE AND RESOLUTION
The following tables show the rms noise, peak-to-peak noise, effective resolution, and noise free (peak-to-peak) resolution of the AD7193 for various output data rates and gain settings with chop disabled for the sinc4 and sinc3 filters and for fast settling mode. The numbers given are for the bipolar input range with an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is calculated based on peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. With chop enabled, the resolution improves by 0.5 bits.
SINC4 CHOP DISABLED
Table 6. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 26.7 13.3 4.17 1.67 0.83 1 340 410 430 950 1000 1600 2300 4200 7100 26,000 8 53 67 76 150 160 250 340 610 1000 3400 16 34 40 45 80 90 140 190 350 570 1700 Gain of 32 18 24 28 50 54 83 120 210 350 910 64 12 14 16 37 40 63 90 160 260 530 128 11 13 15 31 35 55 79 140 230 380
Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 26.7 13.3 4.17 1.67 0.83 1 2200 2700 3000 6000 6600 10,000 14,000 28,000 49,000 175,000 8 340 410 450 890 1000 1500 2200 4100 7000 23,000 16 190 230 260 500 560 920 1300 2400 3800 12,000 Gain of 32 110 130 150 320 350 540 800 1400 2400 6100 64 70 90 100 230 250 400 600 1000 1800 3500 128 65 85 95 200 220 370 530 900 1700 2600
Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1
1
Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800
Settling Time (ms) 852.5 533 400 80 66.7 26.7 13.3 4.17 1.67 0.83
1 24 (22.1) 24 (21.8) 24 (21.7) 23.3 (20.7) 23.3 (20.5) 22.6 (19.9) 22.1 (19.4) 21.2 (18.4) 20.4 (17.6) 18.6 (15.8)
8 24 (21.8) 24 (21.5) 24 (21.4) 23 (20.4) 22.9 (20.3) 22.3 (19.7) 21.8 (19.1) 21 (18.2) 20.3 (17.4) 18.5 (15.7)
Gain of 1 16 32 24 (21.6) 24 (21.4) 23.9 (21.4) 23.6 (21.2) 23.7 (21.2) 23.4 (21) 22.9 (20.3) 22.6 (19.9) 22.8 (20.1) 22.5 (19.8) 22.1 (19.4) 21.8 (19.1) 21.6 (18.9) 21.3 (18.6) 20.8 (18) 20.5 (17.8) 20.1 (17.3) 19.8 (17) 18.5 (15.7) 18.4 (15.6)
64 23.6 (21.1) 23.4 (20.7) 23.2 (20.6) 22 (19.4) 21.9 (19.3) 21.2 (18.6) 20.7 (18) 19.9 (17.3) 19.2 (16.4) 18.2 (15.4)
128 22.8 (20.2) 22.5 (19.8) 22.3 (19.6) 21.3 (18.6) 21.1 (18.4) 20.4 (17.7) 19.9 (17.2) 19.1 (16.4) 18.4 (15.5) 17.6 (14.9)
The output peak-to-peak (p-p) resolution is listed in parentheses.
Rev. A | Page 15 of 56
AD7193
SINC3 CHOP DISABLED
Table 9. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.625 1 340 410 490 1000 1100 1700 2400 6400 115,000 860,000 8 58 72 90 160 170 260 350 870 14,000 110,000 16 35 41 45 85 95 150 200 470 7000 54,000 Gain of 32 20 25 28 54 59 88 130 270 3600 27,000 64 13 16 18 38 41 66 94 190 1800 14,000 128 11 14 16 34 37 59 85 160 950 7000
Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.625 1 2200 2700 3000 6400 7000 11,000 16,000 40,000 730,000 5,700,000 8 350 450 520 990 1100 1700 2300 5700 93,000 730,000 16 220 270 310 540 610 980 1400 3100 47,000 360,000 Gain of 32 130 160 180 370 390 580 860 1800 24,000 180,000 64 80 100 120 250 270 440 630 1300 12,000 93,000 128 65 88 100 230 250 390 560 1100 6100 45,000
Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1
1
Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800
Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.625
Gain of 1 1 24 (22.1) 24 (21.8) 24 (21.7) 23.3 (20.6) 23.1 (20.4) 22.5 (19.8) 22 (19.3) 20.6 (17.9) 16.5 (13.7) 13.5 (10.8) 8 24 (21.8) 24 (21.4) 23.8 (21.2) 22.9 (20.3) 22.8 (20.1) 22.2 (19.5) 21.8 (19.1) 20.5 (17.7) 16.4 (13.7) 13.5 (10.7) 16 24 (21.4) 23.9 (21.1) 23.7 (20.9) 22.9 (20.1) 22.7 (20) 22 (19.3) 21.6 (18.8) 20.3 (17.6) 16.4 (13.7) 13.5 (10.7) 32 23.9 (21.2) 23.6 (20.9) 23.4 (20.7) 22.5 (19.7) 22.3 (19.6) 21.8 (19) 21.2 (18.5) 20.1 (17.4) 16.4 (13.7) 13.5 (10.7) 64 23.5 (20.9) 23.2 (20.6) 23 (20.3) 22 (19.3) 21.9 (19.1) 21.2 (18.4) 20.7 (17.9) 19.6 (16.9) 16.4 (13.7) 13.5 (10.7) 128 22.8 (20.2) 22.4 (19.8) 22.2 (19.6) 21.1 (18.4) 21 (18.3) 20.3 (17.6) 19.8 (17.1) 18.9 (16.1) 16.4 (13.6) 13.5 (10.7)
The output peak-to-peak (p-p) resolution is listed in parentheses.
Rev. A | Page 16 of 56
AD7193
FAST SETTLING
Table 12. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal) 96 30 6 5 2 1 Average 16 16 16 16 16 16 Output Data Rate (Hz) 2.63 8.4 42.10 50.53 126.32 252.63 Settling Time (ms) 380 118.75 23.75 19.79 7.92 3.96 1 380 620 1300 1500 2300 3400 8 87 140 270 280 380 520 16 52 71 150 160 210 290 Gain of 32 33 43 82 88 130 180 64 15 30 56 61 88 130 128 11 21 47 50 77 110
Table 13. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal) 96 30 6 5 2 1 Average 16 16 16 16 16 16 Output Data Rate (Hz) 2.63 8.4 42.10 50.53 126.32 252.63 Settling Time (ms) 380 118.75 23.75 19.79 7.92 3.96 Gain of 1 2500 4000 8500 9500 14,000 22,000 8 450 900 1800 1900 2800 3800 16 260 470 950 1000 1500 2000 32 180 280 540 580 850 1200 64 100 190 360 390 580 820 128 70 130 300 330 510 740
Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word (Decimal) 96 30 6 5 2 1
1
Average 16 16 16 16 16 16
Output Data Rate (Hz) 2.63 8.4 42.10 50.53 126.32 252.63
Settling Time (ms) 380 118.75 23.75 19.79 7.92 3.96
1 24 (21.9) 23.9 (21.3) 22.9 (20.2) 22.7 (20) 22.1 (19.4) 21.5 (18.8)
8 23.8 (21.4) 23.6 (20.4) 22.1 (19.4) 22.1 (19.3) 21.6 (18.8) 21.2 (18.3)
Gain of 1 16 32 23.5 (21.2) 23.2 (20.7) 23.1 (20.3) 22.8 (20.1) 22 (19.3) 21.9 (19.1) 21.9 (19.3) 21.8 (19) 21.5 (18.7) 21.2 (18.5) 21 (18.3) 20.7 (18)
64 23.2 (20.6) 22.3 (19.6) 21.4 (18.7) 21.3 (18.6) 20.8 (18) 20.2 (17.5)
128 22.8 (20.1) 21.8 (19.2) 20.7 (18) 20.6 (17.9) 20 (17.2) 19.4 (16.7)
The output peak-to-peak (p-p) resolution is listed in parentheses.
Rev. A | Page 17 of 56
AD7193 ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set, implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. Table 15. Register Summary
Register Communications Status Mode Addr. 00 00 01 Dir. W R R/W Default 00 80 080060 Bit 7 0 RDY Bit 6 R/W ERR Bit 5 Bit 4 Bit 3 Register address NOREF Parity CHD3 DAT_STA CLK_DIV FS4 REFSEL CH4 BUF D20 D12 D4 X GP10EN OF20 OF12 OF4 FS20 FS12 FS4 CLK1 Single FS3 0 CH3 U/B D19 D11 D3 0 P3DAT OF19 OF11 OF3 FS19 FS11 FS3 Bit 2 CREAD CHD2 CLK0 REJ60 FS2 Pseudo CH2 G2 D18 D10 D2 0 P2DAT OF18 OF10 OF2 FS18 FS10 FS2 Bit 1 0 CHD1 AVG1 FS9 FS1 Short CH1 G1 D17 D9 D1 1 P1DAT OF17 OF9 OF1 FS17 FS9 FS1 Bit 0 0 CHD0 AVG0 FS8 FS0 (LSB) TEMP CH0 G0 (LSB) D16 D8 D0 (LSB) 0 P0DAT OF16 OF8 OF0 (LSB) FS16 FS8 FS0 (LSB)
Configuration
02
R/W
000117
Mode select SINC3 0 FS7 FS6 Chop (MSB) 0 CH7 CH6 Burn REFDET D23 (MSB) D15 D7 X 0 OF23 (MSB) OF15 OF7 FS23 (MSB) FS15 FS7 D22 D14 D6 X BPDSW OF22 OF14 OF6 FS22 FS14 FS6
ENPAR FS5 0 CH5 0 D21 D13 D5 X GP32EN OF21 OF13 OF5 FS21 FS13 FS5
Data
03
R
000000
ID GPOCON Offset
04 05 06
R R/W R/W
X2 00 800000
Full Scale
07
R/W
5XXXX0
Rev. A | Page 18 of 56
AD7193
COMMUNICATIONS REGISTER
RS2, RS1, RS0 = 000
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determine whether the next operation is a read or write operation and in which register this operation occurs. For read or write operations, when the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 16 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.
CR7 WEN(0)
CR6 R/W(0)
CR5 RS2(0)
CR4 RS1(0)
CR3 RS0(0)
CR2 CREAD(0)
CR1 0(0)
CR0 0(0)
Table 16. Communications Register (CR) Bit Designations
Bit Location CR7 Bit Name WEN Description Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is the first bit written, the part does not clock onto subsequent bits in the register; rather, it stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface. 0 in this bit location indicates that the next operation is a write to a specified register. 1 in this bit position indicates that the next operation is a read from the designated register. Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication (see Table 17). Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, Instruction 01011100 must be written to the communications register. To disable continuous read, Instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s occur on DIN; therefore, hold DIN low until an instruction is written to the device. These bits must be programmed to Logic 0 for correct operation.
CR6 CR5 to CR3 CR2
R/W RS2 to RS0 CREAD
CR1 to CR0
0
Table 17. Register Selection
RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications register during a write operation Status register during a read operation Mode register Configuration register Data register/data register plus status information ID register GPOCON register Offset register Full-scale register Register Size 8 bits 8 bits 24 bits 24 bits 24 bits/32 bits 8 bits 8 bits 24 bits 24 bits
Rev. A | Page 19 of 56
AD7193
STATUS REGISTER
RS2, RS1, RS0 = 000; Power-On/Reset = 0x80
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read operation, and
SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 Parity(0)
load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 18 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.
SR3 CHD3(0)
SR2 CHD2(0)
SR1 CHD1(0)
SR0 CHD0(0)
Table 18. Status Register (SR) Bit Designations
Bit Location SR7 Bit Name RDY Description Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence of a reference voltage. This bit is cleared when the result written to the data register returns to within the allowed analog input range. The ERR bit is also set during calibrations if the reference source is invalid or if the applied analog input voltages are outside range during system calibrations. No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. Parity check of the data register. If the ENPAR bit in the mode register is set and there is an odd number of 1s in the data register, the parity bit is set. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated.
SR6
ERR
SR5
NOREF
SR4
Parity
SR3 to SR0
CHD3 to CHD0
Rev. A | Page 20 of 56
AD7193
MODE REGISTER
RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060
The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 19 outlines the bit designations for the mode
MR23 MD2(0) MR15 SINC3(0) MR7 FS7(0) MR22 MD1(0) MR14 0 MR6 FS6(1) MR21 MD0(0) MR13 ENPAR(0) MR5 FS5(1) MR20 DAT_STA(0) MR12 CLK_DIV(0) MR4 FS4(0)
register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the RDY bit.
MR19 CLK1(1) MR11 Single(0) MR3 FS3(0)
MR18 CLK0(0) MR10 REJ60(0) MR2 FS2(0)
MR17 AVG1(0) MR9 FS9(0) MR1 FS1(0)
MR16 AVG0(0) MR8 FS8(0) MR0 FS0(0)
Table 19. Mode Register (MR) Bit Designations
Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA Description Mode select bits. These bits select the operating mode of the AD7193 (see Table 20). This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. These bits select the clock source for the AD7193. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7193 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7193. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. Fast settling filter. When this option is selected, the settling time equals one conversion time. In fast settling mode, a first-order average and decimate block is included after the sinc filter. The data from the sinc filter is averaged by 2, 8, or 16. The averaging reduces the output data rate for a given FS word; however, the rms noise improves. The AVG1 and AVG0 bits select the amount of averaging. Fast settling mode can be used for FS words less than 512 only. When the sinc3 filter is selected, the FS word must be less than 256 when averaging by 16. AVG1 AVG0 Average 0 0 No averaging (fast settling mode disabled) 0 1 Average by 2 1 0 Average by 8 1 1 Average by 16 Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set, the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time. For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC whereas the sinc4 filter has a settling time of 4/fADC when chop is disabled. The sinc4 filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes. This bit must be programmed with a Logic 0 for correct operation. Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read.
MR19, MR18
CLK1, CLK0
MR17, MR16
AVG1, AVG0
MR15
SINC3
MR14 MR13
0 ENPAR
Rev. A | Page 21 of 56
AD7193
Bit Location MR12 Bit Name CLK_DIV Description Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this bit to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AVDD is greater than or equal to 4.75 V, it is not compulsory to set the CLK_DIV bit when performing internal full-scale calibrations. Single cycle conversion enable bit. When this bit is set, the AD7193 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. If the average + decimate filter is enabled, this bit (single) does not have an effect on the conversions unless chopping is also enabled. This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise and, therefore, the effective resolution of the device (see Table 6 through Table 14). When chop is disabled, fast settling mode is disabled and continuous conversion mode is selected Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled and fast settling mode disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled (fast settling mode disabled) Output Data Rate = (MCLK/1024)/(N x FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The first notch frequency of the sinc filter is equal to N x Output Data Rate The chopping introduces notches at odd integer multiples of Output Data Rate/2
MR11
Single
MR10
REJ60
MR9 to MR0
FS9 to FS0
Table 20. Operating Modes (MD)
MD2 0 MD1 0 MD0 0 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register until another conversion is performed. RDY remains active (low) until the data is read or another conversion is performed. Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be provided. Power-down mode. In power-down mode, all AD7193 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7193 for settling reasons. The external crystal, if selected, remains active.
0
0
1
0 0
1 1
0 1
Rev. A | Page 22 of 56
AD7193
MD2 1 MD1 0 MD0 0 Mode Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended each time that the gain of a channel is changed to minimize the full-scale error. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing the internal full-scale calibration. System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is recommended each time that the gain of a channel is changed. System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended each time the gain of a channel is changed.
1
0
1
1
1
0
1
1
1
Rev. A | Page 23 of 56
AD7193
CONFIGURATION REGISTER
RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117
The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Table 21 outlines the bit designations for the configuration register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.
CON23 Chop(0) CON15 CH7(0) CON7 Burn(0)
CON22 0(0) CON14 CH6(0) CON6 REFDET(0)
CON21 0(0) CON13 CH5(0) CON5 0(0)
CON20 REFSEL(0) CON12 CH4(0) CON4 BUF(1)
CON19 0(0) CON11 CH3(0) CON3 U/B (0)
CON18 Pseudo(0) CON10 CH2(0) CON2 G2(1)
CON17 Short(0) CON9 CH1(0) CON1 G1(1)
CON16 TEMP(0) CON8 CH0(1) CON0 G0(1)
Table 21. Configuration Register (CON) Bit Designations
Bit Location CON23 Bit Name Chop Description Chop enable bit. When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. These bits must be programmed with a Logic 0 for correct operation. Reference select bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(-). 1 External reference applied between the P1/REFIN2(+) and P0/REFIN2(-) pins. This bit must be programmed with a Logic 0 for correct operation. Pseudo differential analog inputs. The analog inputs can be configured as differential inputs or pseudo differential analog inputs. When the pseudo bit is set to 1, the AD7193 is configured to have eight pseudo differential analog inputs. When pseudo bit is set to 0, the AD7193 is configured to have four differential analog inputs. Channel select bits. These bits select which channels are enabled on the AD7193 (see Table 22 and Table 23). Several channels can be selected, and the AD7193 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected. When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When burn = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active. This bit must be programmed with a Logic 0 for correct operation.
CON22, CON21 CON20
0 REFSEL
CON19 CON18
0 Pseudo
CON17 to CON8
Short, TEMP, CH7 to CH0
CON7
Burn
CON6
REFDET
CON5
0
Rev. A | Page 24 of 56
AD7193
Bit Location CON4 Bit Name BUF Description Enables the buffer on the analog inputs. If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD. Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. Gain select bits. These bits are written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 2.5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 312.5 mV 1 0 0 16 156.2 mV 1 0 1 32 78.125 mV 1 1 0 64 39.06 mV 1 1 1 128 19.53 mV
CON3
U/B
CON2 to CON0
G2 to G0
Table 22. Channel Selection (Pseudo Bit = 0)
Channel Enable Bits in the Configuration Register Short TEMP CH7 CH6 CH5 CH4 CH3 CH2 CH1 1 1 1 1 1 1 1 1 1 CH0 1 Channel Enabled Positive Negative Input AIN(+) Input AIN(-) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 Temperature sensor AIN2 AIN2 Status Register Bits CHD[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Calibration Register Pair 0 1 2 3 0 1 2 3 0
Table 23. Channel Selection (Pseudo Bit = 1)
Channel Enable Bits in the Configuration Register Short TEMP CH7 CH6 CH5 CH4 CH3 CH2 CH1 1 1 1 1 1 1 1 1 1 CH0 1 Channel Enabled Positive Negative Input AIN(+) Input AIN(-) AIN1 AINCOM AIN2 AINCOM AIN3 AINCOM AIN4 AINCOM AIN5 AINCOM AIN6 AINCOM AIN7 AINCOM AIN8 AINCOM Temperature sensor AINCOM AINCOM Status Register Bits CHD[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Calibration Register Pair 0 1 2 3 4 4 4 4 0
Rev. A | Page 25 of 56
AD7193
DATA REGISTER
RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000
The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. Upon completion of a read operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the four LSBs of the status register (CHD3 to CHD0) identify the channel from which the conversion originated.
GPOCON REGISTER
RS2, RS1, RS0 = 101; Power-On/Reset = 0x00
The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general-purpose digital outputs. Table 24 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.
ID REGISTER
RS2, RS1, RS0 = 100; Power-On/Reset = 0xX2
The identification number for the AD7193 is stored in the ID register. This is a read-only register.
GP7 0(0) GP6 BPDSW(0) GP5 GP32EN(0) GP4 GP10EN(0) GP3 P3DAT(0) GP2 P2DAT(0) GP1 P1DAT(0) GP0 P0DAT(0)
Table 24. GPOCON Register (GP) Bit Designations
Bit Location GP7 GP6 Bit Name 0 BPDSW Description This bit must be programmed with a Logic 0 for proper operation. Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power-down switch. When the ADC is placed in powerdown mode, the bridge power-down switch remains active. Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the P3 and P2 digital outputs are active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored. Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the P1 and P0 digital outputs are active. The P1 and P0 pins can be used as a reference input to REFIN2 when the REFSEL bit in the configuration register is set to 1. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set. Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set. Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set. Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set.
GP5
GP32EN
GP4
GP10EN
GP3
P3DAT
GP2
P2DAT
GP1
P1DAT
GP0
P0DAT
Rev. A | Page 26 of 56
AD7193
OFFSET REGISTER
RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000)
The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7193 has five offset registers. In differential mode, each channel has a dedicated offset register. In pseudo differential mode, Channel AIN1, Channel AIN2, Channel AIN3, and Channel AIN4 have dedicated registers whereas the remaining channels share an offset register (see Table 22 and Table 23). Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7193 must be placed in powerdown mode or idle mode when writing to the offset register.
FULL-SCALE REGISTER
RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0
The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7193 has five fullscale registers. In differential mode, each channel has a dedicated full-scale register. In pseudo differential mode, the AIN1, AIN2, AIN3, and AIN4 channels have dedicated registers whereas the remaining channels share a full-scale register (see Table 22 and Table 23). The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured at power-on with factory calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device has different default coefficients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to.
Rev. A | Page 27 of 56
AD7193 ADC CIRCUIT INFORMATION
5V
REFIN1(+) AGND IN+ OUT- OUT+ AIN1 AIN2 AIN3 AIN4 AIN5 MUX AIN6 AIN7 AIN8 AINCOM REFIN1(-) BPDSW AGND
AVDD AVDD
DVDD DGND
REFERENCE DETECT
IN-
PGA
MODULATOR AND FILTER - ADC
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY DIN SCLK CS SYNC P3 P2
AGND
TEMP SENSOR
CALIBRATION
AD7193
CLOCK CIRCUITRY
08367-023
MCLK1 MCLK2
P0/REFIN2(-) P1/REFIN2(+)
Figure 21. Basic Connection Diagram
OVERVIEW
The AD7193 is an ultralow noise ADC that incorporates a - modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gage applications. Figure 21 shows the basic connections required to operate the part.
Sigma-Delta () ADC and Filter
The AD7193 contains a fourth-order - modulator followed by a digital filter. The device has several filter options * * * * * Sinc4 Sinc3 Chop enabled/disabled Fast settling Zero latency
Analog Inputs
The device can be configured to have four differential or eight pseudo differential analog inputs. The analog inputs can be buffered or unbuffered.
Serial Interface
The AD7193 has a 4-wire SPI interface. The on-chip registers are accessed via the serial interface.
Multiplexer
The on-chip multiplexer increases the channel count of the device. Because the multiplexer is included on chip, any channel changes are synchronized with the conversion process.
Clock
The AD7193 has an internal 4.92 MHz clock. Either this clock or an external clock can be used as the clock source to the AD7193. The internal clock can also be made available on a pin if a clock source is required for external circuitry.
PGA
The analog input signal can be amplified using the PGA. The PGA allows gains of 1, 8, 16, 32, 64, and 128.
Bridge Power-Down Switch
External circuitry such as strain gages or bridges can be powered up/down using the bridge power-down switch.
Reference Detect
The AD7193 is capable of monitoring the external reference. If the reference is not present, a flag is set in the status register of the device.
Temperature Sensor
The on-chip temperature sensor monitors the die temperature.
Burnout Currents
Two 500 nA burnout currents are included on-chip to detect the presence of the external sensor.
Digital Outputs
The AD7193 has four general-purpose digital outputs. These can be used for driving external circuitry. For example, an external multiplexer can be controlled by these outputs.
Calibration
Both internal and system calibration are included on chip; therefore, the user has the option of removing offset/gain errors internal to the AD7193 only, or removing the offset/gain errors of the complete end system.
Rev. A | Page 28 of 56
AD7193
ANALOG INPUT CHANNEL
The AD7193 has four differential/eight pseudo differential analog input channels that can be buffered or unbuffered. In the buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive type sensors such as strain gages or resistance temperature detectors (RTDs). When BUF = 0, the part is operated in the unbuffered mode. This results in a higher analog input current. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the ADC input. Table 25 shows the allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20-bit level is introduced. Table 25. External R-C Combination for No 20-Bit Gain Error
C (pF) 50 100 500 1000 5000 R () 1.4 k 850 300 230 30
The analog input range must be limited to (AVDD - 1.25 V)/gain because the PGA requires some headroom. Therefore, if VREF = AVDD = 5 V, the maximum analog input that can be applied to the AD7193 is 0 V to 3.75 V/gain in unipolar mode or 3.75 V/gain in bipolar mode.
REFERENCE
The ADC has a fully differential input capability for the reference channel. In addition, the user has the option of selecting one of two external reference options (REFIN1() or REFIN2()). The reference source for the AD7193 is selected using the REFSEL bit in the configuration register. The REFIN2() pins are dual purpose: they can function as two general-purpose output pins or as reference pins. When the REFSEL bit is set to 1, these pins automatically function as reference pins. The common-mode range for these differential inputs is from AGND to AVDD. The reference voltage REFIN (REFINx(+) - REFINx(-)) is AVDD nominal, but the AD7193 is functional with reference voltages from 1 V to AVDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7193 is used in a nonratiometric application, a low noise reference should be used. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. R-C values similar to those in Table 25 are recommended for the reference inputs. Deriving the reference input voltage from an external resistor means that the reference input sees significant external source impedance. External decoupling on the REFINx pins is not recommended in this type of circuit configuration. Conversely, if large decoupling capacitors are used on the reference inputs, there should be no resistors in series with the reference inputs. Recommended 2.5 V reference voltage sources for the AD7193 include the ADR421 and ADR431, which are low noise references. These references tolerate decoupling capacitors on REFINx(+) without introducing gain errors in the system. Figure 22 shows the recommended connections between the ADR421 and the AD7193.
AVDD
2
The absolute input voltage range in buffered mode is restricted to a range between AGND + 250 mV and AVDD - 250 mV. Care must be taken in setting up the common-mode voltage to not exceed these limits; otherwise, linearity and noise performance degrade. The absolute input voltage in unbuffered mode includes the range between AGND - 50 mV and AVDD + 50 mV. The negative absolute input voltage limit allows the possibility of monitoring small true bipolar signals with respect to AGND.
PROGRAMMABLE GAIN ARRAY (PGA)
When the gain stage is enabled, the output from the buffer is applied to the input of the PGA. The presence of the PGA means that signals of small amplitude can be gained within the AD7193 and still maintain excellent noise performance. For example, when the gain is set to 128, the rms noise is 11 nV, typically, when the output data rate is 4.7 Hz, which is equivalent to 22.7 bits of effective resolution or 20 bits of noise free resolution. The AD7193 can be programmed to have a gain of 1, 8, 16, 32, 64, or 128 by using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V, and the bipolar ranges are from 19.53 mV to 2.5 V.
ADR421
AD7193
VIN
VOUT 6 4.7F
REFINx(+)
0.1F
10F
Figure 22. ADR421 to AD7193 Connections
Rev. A | Page 29 of 56
08367-124
4
GND
TRIM 5
REFINx(-)
AD7193
REFERENCE DETECT
The AD7193 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. This feature is enabled when the REFDET bit in the configuration register is set to 1. If the voltage between the selected REFINx(+) and REFINx(-) pins is less than 0.3 V, the AD7193 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set to 1. When the voltage between the selected REFINx(+) and REFINx(-) pins is greater than 0.6 V, the AD7193 detects a valid reference so the NOREF bit is set to 0. The operation of the NOREF bit is undefined when the voltage between the selected REFINx(+) and REFINx(-) pins is between 0.3 V and 0.6 V. If the AD7193 is performing normal conversions and the NOREF bit becomes active, the conversion result is all 1s. Therefore, it is not necessary to continuously monitor the status of the NOREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC data register is all 1s. If the AD7193 is performing either an offset or full-scale calibration and the NOREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle. When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N - 1 x [(AIN x Gain/VREF) + 1] where: AIN is the analog input voltage. Gain is the PGA setting (1 to 128). N = 24.
BURNOUT CURRENTS
The AD7193 contains two 500 nA constant current generators, one sourcing current from AVDD to AIN(+) and one sinking current from AIN(-) to AGND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the burnout current enable (burn) bit in the configuration register. These currents can be used to verify that an external transducer remains operational before attempting to take measurements on that channel. After the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. It takes some time for the burnout currents to detect an open circuit condition because the currents must charge any external capacitors. There are several reasons that a fault condition is detected: the front-end sensor may be either open circuit or overloaded, or the reference may be absent and the NOREF bit in the status register is set, thus clamping the data to all 1s. The user must check these three cases before making a determination. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. The current sources work over the normal absolute input voltage range specifications when the analog inputs are buffered and chop is disabled.
BIPOLAR/UNIPOLAR CONFIGURATION
The analog input to the AD7193 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system AGND. In pseudo differential mode, signals are referenced to AINCOM, whereas in differential mode, signals are referenced to the negative input of the differential pair. For example, if AINCOM is 2.5 V and the AD7193 AIN1 analog input is configured for unipolar mode with a gain of 2, the input voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V reference is used. If AINCOM is 2.5 V and the AD7193 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1.25 V to 3.75 V. The bipolar/unipolar option is chosen by programming the U/B bit in the configuration register.
CHANNEL SEQUENCER
The AD7193 includes a channel sequencer, which simplifies communications with the device in multichannel applications. The sequencer also optimizes the channel throughput of the device because the sequencer switches channels at the optimum rate rather than waiting for instructions via the SPI interface. Bit CH0 to Bit CH7 in the configuration register are used to enable the required analog input channels. The analog inputs must be configured for differential mode or pseudo differential mode using the pseudo bit in the configuration register. The temperature sensor is enabled using the TEMP bit in the configuration. An internal short can also be selected using the short bit in the configuration register. In continuous conversion mode, the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The DOUT/RDY pin indicates when a valid conversion is
DATA OUTPUT CODING
When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 000...000, a midscale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = (2N x AIN x Gain)/VREF
Rev. A | Page 30 of 56
AD7193
available on each channel. When several channels are enabled, the contents of the status register should be attached to the 24-bit word allowing the user to identify the channel that corresponds to each conversion. The four LSBs of the status register indicate the channel to which the conversion corresponds. Table 22 and Table 23 show the channel options for differential mode and pseudo differential mode with the corresponding channel ID values in the status register. To attach the status register value to the conversion, Bit DAT_STA in the mode register should be set to 1. When several channels are enabled, the ADC allows the complete filter settling time to generate a valid conversion each time that the channel is changed. The AD7193 automatically takes care of this through the following sequence: 1. 2. 3. 4. 5. When a channel is selected, the modulator and filter are reset. The AD7193 allows the complete settling time to generate a valid conversion. DOUT/RDY indicates when a valid conversion is available. The AD7193 selects the next enabled channel and converts on that channel. The user can read the data register while the ADC is performing the conversion on the next channel.
DIGITAL INTERFACE
As indicated in the On-Chip Registers section, the programmable functions of the AD7193 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface of the part. Read access to the on-chip registers is also provided by this interface. All communication with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation, and it determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part begins with a write operation to the communications register, followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. The serial interface of the AD7193 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers and DOUT/RDY is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/RDY pin also functions as a data ready signal, the line going low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. CS is used to select a device. It can be used to decode the AD7193 in systems where several components are connected to the serial bus. Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7193 using CS to decode the part. Figure 3 shows the timing for a read operation from the output shift register of the AD7193, and Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times even though the DOUT/RDY line returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7193. The end of the conversion can be monitored using the RDY bit or pin. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers.
The time required to read a valid conversion from all enabled channels is equal to tSETTLE x Number of Enabled Channels For example, if the sinc4 filter is selected, chop is disabled, and zero latency is disabled, the settling time for each channel equals tSETTLE = 4/fADC where fADC is the output data rate when continuously converting on a single channel. Therefore, the time required to read all enabled channels is (4x Number of Enabled Channels)/fADC
RDY CONVERSIONS
08367-060
CHANNEL A
CHANNEL B 1/fADC
CHANNEL C
Figure 23. Channel Sequencer
Rev. A | Page 31 of 56
AD7193
The AD7193 can be operated with CS used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. The serial interface can be reset by writing a series of 1s to the DIN input. If a Logic 1 is written to the AD7193 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface is lost due to a software error or a glitch in the system. Reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 s before addressing the serial interface. The AD7193 can be configured to continuously convert or to perform a single conversion (see Figure 24 through Figure 26). DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high. If CS is low, DOUT/RDY remains high until another conversion is initiated and completed. The data register can be read several times, if required, even when DOUT/RDY has gone high. If several channels are enabled, the ADC sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/RDY goes high and remains high until a valid conversion is available. As soon as the conversion is available, DOUT/RDY goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to powerdown mode. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The four LSBs of the status register indicate the channel to which the conversion corresponds.
Single Conversion Mode
In single conversion mode, the AD7193 is placed in powerdown mode after conversions. When a single conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the mode register, the AD7193 powers up, performs a single conversion, and then returns to power-down mode. The onchip oscillator requires 1 ms, approximately, to power up.
CS
DIN
0x08
0x280060
0x58
DATA DOUT/RDY
SCLK
Figure 24. Single Conversion
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AD7193
Continuous Conversion Mode
Continuous conversion is the default power-up mode. The AD7193 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost.
CS
When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion on each channel per loop. The data register is updated as soon as each conversion is available. The DOUT/RDY pin pulses low each time a conversion is available. The user can then read the conversion while the ADC converts on the next enabled channel. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The status register indicates the channel to which the conversion corresponds.
0x58 DIN
0x58
DOUT/RDY
DATA
DATA
SCLK
Figure 25. Continuous Conversion
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AD7193
Continuous Read
Rather than write to the communications register each time a conversion is complete to access the data, the AD7193 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is automatically placed on the DOUT/RDY line when a conversion is complete. The ADC should be configured for continuous conversion mode. When DOUT/RDY goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC; the data conversion is then placed on the DOUT/RDY line. When the conversion is read, DOUT/RDY returns high until the next conversion is available. In this mode, the data can be read only once. The user must also ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7193 to read the word, the serial output register is reset when the next
CS
conversion is complete, and the new conversion is placed in the output serial register. To exit the continuous read mode, Instruction 01011000 must be written to the communications register while the RDY pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. When several channels are enabled, the ADC continuously steps through the enabled channels and performs one conversion on each channel each time that it is selected. DOUT/RDY pulses low when a conversion is available. When the user applies sufficient SCLK pulses, the data is automatically placed on the DOUT/RDY pin. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion. The status register indicates the channel to which the conversion corresponds.
0x5C DIN
DOUT/RDY
DATA
DATA
DATA
SCLK
Figure 26. Continuous Read
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AD7193
RESET
The circuitry and serial interface of the AD7193 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 s before accessing any of the on-chip registers. A reset is useful if the serial interface loses synchronization due to noise on the SCLK line.
ENABLE PARITY
When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. To append the contents of the status register to each conversion read, the DAT_STA bit in the mode register should be set to 1. For each conversion read, the parity bit in the status register is programmed so that the overall number of 1s transmitted in the 24-bit data-word is even. Therefore, for example, if the 24-bit conversion contains 11 ones (binary format), the parity bit is set to 1 so that the total number of ones in the serial transmission is even. If the microprocessor receives an odd number of 1s, it knows that the data received has been corrupted. The parity function does not ensure that all errors are detected. For example, two bits of corrupt data can result in the microprocessor receiving an even number of ones. Therefore, an error condition is not detected.
SYSTEM SYNCHRONIZATION
The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of SYNC. SYNC needs to be taken low for at least four master clock cycles to implement the synchronization function. If multiple AD7193 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. A falling edge on the SYNC pin resets the digital filter and the analog modulator and places the AD7193 into a consistent, known state. While the SYNC pin is low, the AD7193 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. In a system using multiple AD7193 devices, a common signal to their SYNC pins synchronizes their operation. This is normally done after each AD7193 has performed its own calibration or has calibration coefficients loaded into its calibration registers. The conversions from the AD7193s are then synchronized. The part is taken out of reset on the master clock falling edge following the SYNC low-to-high transition. Therefore, when multiple devices are being synchronized, the SYNC pin should be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle. The SYNC pin can also be used as a start conversion command. In this mode, the rising edge of SYNC starts conversion, and the falling edge of RDY indicates when the conversion is complete. The settling time of the filter has to be allowed for each data register update. For example, if the ADC is configured to use the sinc4 filter, zero latency is disabled, and chop is disabled, the settling time equals 4/fADC, where fADC is the output data rate when continuously converting on a single channel.
CLOCK
The AD7193 includes an internal 4.92 MHz clock on chip. This internal clock has a tolerance of 4%. Either the internal clock or an external crystal/clock can be used as the clock source to the AD7193. The clock source is selected using the CLK1 and CLK0 bits in the mode register. When an external crystal is used, it must be connected across the MCLK1 and MCLK2 pins. The crystal manufacturer recommends the load capacitances required for the crystal. The MCLK1 and MCLK2 pins of the AD7193 have a capacitance of 15 pF, typically. If an external clock source is used, the clock source must be connected to the MCLK2 pin, and the MCLK1 pin can remain floating. The internal clock can also be made available at the MCLK2 pin. This is useful when several ADCs are used in an application and the devices must be synchronized. The internal clock from one device can be used as the clock source for all ADCs in the system. Using a common clock, the devices can be synchronized by applying a common reset to all devices, or the SYNC pin can be pulsed.
BRIDGE POWER-DOWN SWITCH
In bridge applications such as strain gages and load cells, the bridge itself consumes the majority of the current in the system. For example, a 350 load cell requires 15 mA of current when excited with a 5 V supply. To minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power-down switch. Figure 21 shows how the bridge power-down switch is used. The switch can withstand 30 mA of continuous current, and it has an on resistance of 10 maximum.
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AD7193
TEMPERATURE SENSOR
Embedded in the AD7193 is a temperature sensor. This is selected using the TEMP bit in the configuration register. When the TEMP bit is set to 1, the temperature sensor is enabled. When the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 when the temperature is 0 Kelvin, theoretically. A one-point calibration is needed to obtain the optimum performance from the sensor. Therefore, a conversion at 25C should be recorded and the sensitivity calculated. The sensitivity is 2815 codes/C, approximately. The equation for the temperature sensor is Temperature (K) = (Conversion - 0x800000)/2815 K Temperature (C) = Temperature (K) - 273 Following the one-point calibration, the internal temperature sensor has an accuracy of 2C, typically. To start a calibration, write the relevant value to the MD2 to MD0 bits. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding calibration registers are updated, the RDY bit in the status register is reset, the DOUT/RDY pin returns low (if CS is low), and the AD7193 reverts to idle mode. During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the calibration mode. In this way, errors external to the ADC are removed. From an operational point of view, treat a calibration like another ADC conversion. A zero-scale calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the DOUT/RDY pin to determine the end of calibration via a polling sequence or an interrupt-driven routine. With chop disabled, both an internal zero-scale calibration and a system zero-scale calibration require a time equal to the settling time, tSETTLE (4/fADC for the sinc4 filter and 3/fADC for the sinc3 filter). With chop enabled, an internal zero-scale calibration is not needed because the ADC itself minimizes the offset continuously. However, if an internal zero-scale calibration is performed, the settling time, tSETTLE (2/fADC), is required to perform the calibration. Similarly, a system zero-scale calibration requires a time of tSETTLE to complete. To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. For a gain of 1, the time required for an internal full-scale calibration is equal to tSETTLE. For higher gains, the internal full-scale calibration requires a time of 2 x tSETTLE. A full-scale calibration is recommended each time the gain of a channel is changed to minimize the full-scale error. A system full-scale calibration requires a time of tSETTLE. With chop disabled, the zero-scale calibration (internal or system zero-scale) should be performed before the system full-scale calibration is initiated. An internal zero-scale calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. An internal full-scale calibration can be performed at any output data rate for which the filter word, FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent of the 10-bit word written to Bit FS9 to Bit FS0 in the mode register. Therefore, internal full-scale calibrations can be performed at output data rates such as 10 Hz or 50 Hz when chop is disabled. Using these lower output data rates results in better calibration accuracy.
LOGIC OUTPUTS
The AD7193 has four general-purpose digital outputs: P0, P1, P2, and P3. These are enabled using the GP32EN and GP10EN bits in the GPOCON register. The pins can be pulled high or low using the P0DAT to P3DAT bits in the GPOCON register; that is, the value at the pin is determined by the setting of the P0DAT to P3DAT bits. The logic levels for these pins are determined by AVDD rather than by DVDD. When the GPOCON register is read, Bit P0DAT to Bit P3DAT reflect the actual value at the pins; this is useful for short-circuit detection. These pins can be used to drive external circuitry, for example, an external multiplexer. If an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the AD7193 general-purpose output pins. The general-purpose output pins can be used to select the active multiplexer pin. Because the operation of the multiplexer is independent of the AD7193, the AD7193 modulator and filter should be reset using the SYNC pin or by a write to the mode or configuration register each time that the multiplexer channel is changed.
CALIBRATION
The AD7193 provides four calibration modes that can be programmed via the mode bits in the mode register. These modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. A calibration can be performed at any time by setting the MD2 to MD0 bits in the mode register appropriately. A calibration should be performed when the gain is changed. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient.
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AD7193
The offset error is, typically, 150 V/gain. If the gain is changed, it is advisable to perform a calibration. A zero-scale calibration (an internal zero-scale calibration or a system zero-scale calibration) reduces the offset error to the order of the noise. The gain error of the AD7193 is factory calibrated at a gain of 1 with a 5 V power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically, at 5 V. Table 26 shows the typical uncalibrated gain error for the different gain settings. Table 26. Typical Precalibration Gain Error vs. Gain
Gain 8 16 32 64 128 Precalibration Gain Error (%) -0.11 -0.20 -0.23 -0.29 -0.39
An internal full-scale calibration reduces the gain error to 0.001%, typically, when the gain is equal to 1. For higher gains, the gain error postinternal full-scale calibration is 0.003%, typically when AVDD is equal to or higher than 4.75 V. When AVDD is less than 4.75 V, the gain error after internal full-scale calibration is 0.005%, typically. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing internal full-scale calibrations. This increases the calibration time by a factor of 2. The accuracy of the internal full-scale calibration is further increased if chop is enabled and a low output data rate is used while performing the calibration. A system full-scale calibration reduces the gain error to the order of the noise irrespective of the analog power supply voltage. The AD7193 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to the registers. The values in the calibration registers are 24 bits wide. The span and offset of the part can also be manipulated using the registers.
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AD7193 DIGITAL FILTER
The AD7193 offers a lot of flexibility in the digital filter. The device has five filter options. The device can be operated with a sinc3 or sinc4 filter, chop can be enabled or disabled, and zero latency can be enabled. Finally, an averaging block can be included after the sinc filter, which gives a fast settling mode. The option selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection. The following sections describe each filter type, indicating the available output data rates for each filter option. The filter response, along with the settling time and 50 Hz/60 Hz rejection, is also discussed. When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input. Therefore, it continues to output conversions at the programmed output data rate. However, it is at least four conversions later before the output data accurately reflect the analog input. If the step change occurs while the ADC is processing a conversion, then the ADC takes five conversions after the step change to generate a fully settled result.
ANALOG INPUT FULLY SETTLED ADC OUTPUT
08367-026
SINC4 FILTER (CHOP DISABLED)
When the AD7193 is powered up, the sinc4 filter is selected by default and chop is disabled. This filter gives excellent noise performance over the complete range of output data rates. It also gives the best 50 Hz/60 Hz rejection, but it has a long settling time.
ADC
1/fADC
Figure 29. Asynchronous Step Change in Analog Input
The 3 dB frequency for the sinc4 filter is equal to f3dB = 0.23 x fADC Table 27 gives some examples of the relationship between the values in Bits FS[9:0] and the corresponding output data rate and settling time. Table 27. Examples of Output Data Rates and the Corresponding Settling Time
FS[9:0] 480 96 80 Output Data Rate (Hz) 10 50 60 Settling Time (ms) 400 80 66.6
CHOP
MODULATOR
SINC3/SINC4
POST FILTER
08367-024
Figure 27. Sinc4 Filter (Chop Disabled)
Sinc4 Output Data Rate/Settling Time
The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to fADC = fCLK/(1024 x FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. The settling time for the sinc4 filter is equal to tSETTLE = 4/fADC When a channel change occurs, the modulator and filter are reset. The settling time is allowed to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/fADC.
CHANNEL CONVERSIONS CHANNEL A
CH A CH A CH A
Sinc4 Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, the conversion time when converting on a single channel or when converting on several channels is constant. The user does not need to consider the effects of channel changes on the output data rate. When the channel sequencer is enabled, the AD7193 automatically operates in zero latency mode. The output data rate equals fADC = 1/tSETTLE = fCLK/(4 x 1024 x FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
CHANNEL B
CH B CH B CH B
08367-025
1/fADC
Figure 28. Sinc4 Channel Change
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AD7193
When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC, which is not completely settled (see Figure 30).
ANALOG INPUT FULLY SETTLED ADC OUTPUT
08367-027
Figure 32 shows the frequency response when FS[9:0] is programmed to 80 and the master clock is equal to 4.92 MHz. The output data rate is 60 Hz when zero latency is disabled and 15 Hz when zero latency is enabled. The sinc4 filter provides 60 Hz (1 Hz) rejection of 120 dB minimum, assuming a stable master clock.
0 -10 -20 -30
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110
1/fADC
Figure 30. Sinc4 Zero Latency Operation
Table 28 shows examples of output data rate and the corresponding FS values. Table 28. Examples of Output Data Rates and the Corresponding Settling Time (Zero Latency)
FS[9:0] 480 96 80 Output Data Rate 2.5 Hz 12.5 Hz 15 Hz Settling Time 400 ms 80 ms 66.6 ms
0
30
60
90
120
150
FREQUENCY (Hz)
Figure 32. Sinc4 Filter Response (FS[9:0] = 80)
Sinc4 50 Hz/60 Hz Rejection
Figure 31 shows the frequency response of the sinc4 filter when FS[9:0] is set to 96 and the master clock is 4.92 MHz. With zero latency disabled, the output data rate is equal to 50 Hz. With zero latency enabled, the output data rate is 12.5 Hz. The sinc4 filter provides 50 Hz (1 Hz) rejection in excess of 120 dB minimum, assuming a stable master clock.
0 -10 -20 -30
Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is programmed to 480 and the master clock equals 4.92 MHz. The output data rate is 10 Hz when zero latency is disabled and 2.5 Hz when zero latency is enabled. The sinc4 filter provides 50 Hz (1 Hz) and 60 Hz (1 Hz) rejection of 120 dB minimum, assuming a stable master clock.
0 -10 -20 -30 FILTER GAIN (dB) -40 -50 -60 -70 -80 -90 -100 -110
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110
0
30
60
90
120
150
FREQUENCY (Hz)
Figure 33. Sinc4 Filter Response (FS[9:0] = 480)
0
25
50
75
100
125
150
FREQUENCY (Hz)
Figure 31. Sinc4 Filter Response (FS[9:0] = 96)
08367-028
-120
Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register. When FS[9:0] is set to 96 and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz.
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-120
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-120
AD7193
The output data rate is 50 Hz when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 34 shows the frequency response of the sinc4 filter. The filter provides 50 Hz 1 Hz and 60 Hz 1 Hz rejection of 82 dB minimum, assuming a stable 4.92 MHz master clock.
0 -10 -20 -30
FILTER GAIN (dB)
The 3 dB frequency is equal to f3dB = 0.272 x fADC Table 29 gives some examples of FS settings and the corresponding output data rates and settling times. Table 29. Examples of Output Data Rates and the Corresponding Settling Time
FS[9:0] 480 96 80 Output Data Rate 10 Hz 50 Hz 60 Hz Settling Time 300 ms 60 ms 50 ms
-40 -50 -60 -70 -80 -90 -100 -110 0 25 50 75 100 125 150
08367-031
When a channel change occurs, the modulator and filter reset. The complete settling time is allowed to generate the first conversion after the channel change (see Figure 36). Subsequent conversions on this channel are available at 1/fADC.
CHANNEL CHANNEL A
CH A CH A CH A
CHANNEL B
-120
FREQUENCY (Hz)
CONVERSIONS
CH B CH B CH B
CH B
08367-033
Figure 34. Sinc Filter Response (FS[9:0] = 96, REJ60 = 1)
4
SINC FILTER (CHOP DISABLED)
A sinc3 filter can be used instead of the sinc4 filter. The filter is selected using the SINC3 bit in the mode register. The sinc3 filter is selected when the SINC3 bit is set to 1. This filter has good noise performance when operating with output data rates up to 1 kHz. It has moderate settling time and moderate 50 Hz/60 Hz (1 Hz) rejection.
ADC
3
1/fADC
Figure 36. Sinc3 Channel Change
When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input. Therefore, it continues to output conversions at the programmed output data rate. However, it is at least three conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, the ADC takes four conversions after the step change to generate a fully settled result.
ANALOG INPUT FULLY SETTLED ADC OUTPUT
08367-034
CHOP
MODULATOR
SINC3/SINC4
POST FILTER
08367-032
Figure 35. Sinc3 Filter (Chop Disabled)
Sinc3 Output Data Rate and Settling Time
The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to fADC = fCLK/(1024 x FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. The settling time is equal to tSETTLE = 3/fADC
1/fADC
Figure 37. Asynchronous Step Change in Analog Input
Sinc3 Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, the conversion time when converting on a single channel or when converting on several channels is constant. The user does not need to consider the effects of channel changes on the output data rate. When the channel sequencer is enabled, the AD7193 automatically operates in zero latency mode.
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AD7193
The output data rate equals fADC = 1/ tSETTLE = fCLK/(3 x 1024 x FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC that is not completely settled (see Figure 38).
ANALOG INPUT FULLY SETTLED ADC OUTPUT
Sinc3 50 Hz/60 Hz Rejection
Figure 39 show the frequency response of the sinc3 filter when FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The output data rate is equal to 50 Hz when zero latency is disabled and 16.7 Hz when zero latency is enabled. The sinc3 filter gives 50 Hz 1 Hz rejection of 95 dB minimum for a stable master clock.
0 -10 -20 -30
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 25 50 75 100 125 150 FREQUENCY (Hz)
08367-036 08367-037
1/fADC
08367-035
Figure 39. Sinc3 Filter Response (FS[9:0] = 96)
Figure 38. Sinc Zero Latency Operation
3
Table 30 provides examples of output data rates and the corresponding FS values. Table 30. Examples of Output Data Rates and the Corresponding Settling Time (Zero Latency)
FS[9:0] 480 96 80 Output Data Rate 3.3 Hz 16.7 Hz 20 Hz Settling Time 300 ms 60 ms 50 ms
When FS[9:0] is set to 80 and the master clock equals 4.92 MHz, 60 Hz rejection is achieved (see Figure 40). The output data rate is equal to 60 Hz when zero latency is disabled and 20 Hz when zero latency is enabled. The sinc3 filter has rejection of 95 dB minimum at 60 Hz 1 Hz, assuming a stable master clock.
0 -10 -20 -30
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 30 60 90 120 150
FREQUENCY (Hz)
Figure 40. Sinc3 Filter Response (FS[9:0] = 80)
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AD7193
Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 41. The output data rate is 10 Hz when zero latency is disabled and 3.3 Hz when zero latency is enabled. The sinc3 filter has rejection of 100 dB minimum at 50 Hz 1 Hz and 60 Hz 1 Hz.
0 -10 -20 -30
FILTER GAIN (dB)
CHOP ENABLED (SINC4 FILTER)
With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins are then inverted, and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. With chop enabled, the resolution increases by 0.5 bits.
ADC
-40 -50 -60
-80 -90 -100 -110
0 30 60 90 120 150
08367-038
Figure 43. Chop Enabled
-120
Output Data Rate and Settling Time (Sinc4 Chop Enabled)
For the sinc4 filter, the output data rate is equal to fADC = fCLK/(4 x 1024 x FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.17 Hz to 1200 Hz. The settling time is equal to tSETTLE = 2/fADC Table 31 gives some examples of FS[9:0] values and the corresponding output data rates and settling times. Table 31. Examples of Output Data Rates and the Corresponding Settling Time
FS[9:0] 96 80 Output Data Rate 12.5 Hz 15 Hz Settling Time 160 ms 133 ms
FREQUENCY (Hz)
Figure 41. Sinc3 Filter Response (FS[9:0] = 480)
Simultaneous 50 Hz/60 Hz rejection is also achieved using the REJ60 bit in the mode register. When FS[9:0] is programmed to 96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz for a stable 4.92 MHz master clock. Figure 42 shows the frequency response of the sinc3 filter with this configuration. Assuming a stable clock, the rejection at 50 Hz/60 Hz (1 Hz) is in excess of 67 dB minimum.
0 -10 -20 -30
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110
0 25 50 75 100 125 150
08367-039
-120
FREQUENCY (Hz)
Figure 42. Sinc3 Filter Response (FS[9:0] = 96, REJ60 = 1)
Rev. A | Page 42 of 56
08367-040
-70
CHOP
MODULATOR
SINC3/SINC4
POST FILTER
AD7193
When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/fADC.
CHANNEL CONVERSIONS CHANNEL A
CH A CH A CH A
0 -10 -20 -30
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110 0 25 50 75 FREQUENCY (Hz) 100 125 150
08367-043 08367-044
CHANNEL B
CH B CH B CH B CH B CH B
08367-041
1/fADC
Figure 44. Channel Change (Sinc4 Chop Enabled)
When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, the ADC takes three conversions after the step change to generate a fully settled result.
ANALOG INPUT FULLY SETTLED
-120
Figure 46. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled)
The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 47 is achieved. The output data rate is unchanged but the 50 Hz/ 60 Hz (1 Hz) rejection is increased to 83 dB typically.
0 -10 -20
ADC OUTPUT
08367-042
-30
FILTER GAIN (dB)
1/fADC
4
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 25 50 75 100 125 150
Figure 45. Asynchronous Step Change in Analog Input (Sinc Chop Enabled)
The cutoff frequency f3dB is equal to f3dB = 0.24 x fADC
50 Hz/60 Hz Rejection (Sinc Chop Enabled)
When FS[9:0] is set to 96 and chopping is enabled, the output data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The filter response shown in Figure 46 is obtained. The chopping introduces notches at odd integer multiples of fADC/2. The notches due to the sinc filter in addition to the notches introduced by the chopping mean that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 12.5 Hz. The rejection at 50 Hz/60 Hz 1 Hz is typically 63 dB, assuming a stable master clock.
4
FREQUENCY (Hz)
Figure 47. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
Rev. A | Page 43 of 56
AD7193
CHOP ENABLED (SINC3 FILTER)
With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins invert and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. With chop enabled, the resolution increases by 0.5 bits. Using the sinc3 filter with chop enabled is suitable for output data rates up to 320 Hz.
ADC
If conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, then the ADC takes three conversions after the step change to generate a fully settled result.
ANALOG INPUT FULLY SETTLED
ADC OUTPUT
1/fADC
CHOP MODULATOR SINC3/SINC4 POST FILTER
08367-045
Figure 50. Asynchronous Step Change in Analog Input (Sinc3 Chop Enabled)
The cutoff frequency f3dB is equal to f3dB = 0.24 x fADC
Figure 48. Chop Enabled (Sinc3 Chop Enabled)
Output Data Rate and Settling Time (Sinc3 Chop Enabled)
For the sinc filter, the output data rate is equal to fADC = fCLK/(3 x 1024 x FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.56 Hz to 1600 Hz. The settling time is equal to
3
50 Hz/60 Hz Rejection (Sinc3 Chop Enabled)
When FS[9:0] is set to 96 and chopping is enabled, the filter response shown in Figure 51 is obtained. The output data rate is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping introduces notches at odd integer multiples of fADC/2. The notches due to the sinc filter in addition to the notches introduced by the chopping means that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 16.7 Hz. The rejection at 50 Hz/60 Hz 1 Hz is typically 53 dB, assuming a stable master clock.
0 -10 -20 -30
FILTER GAIN (dB)
tSETTLE = 2/fADC Table 32. Examples of Output Data Rates and the Corresponding Settling Time (Chop Enabled, Sinc3 Filter)
FS[9:0] 96 80 Output Data Rate 16.7 Hz 20 Hz Settling Time 120 ms 100 ms
-40 -50 -60 -70 -80 -90 -100 -110 0 25 50 75 100 125 150
08367-048
When a channel change occurs, the modulator and filter are reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/fADC.
CHANNEL CONVERSIONS CHANNEL A
CH A CH A CH A
-120
FREQUENCY (Hz)
Figure 51. Sinc3 Filter Response (FS[9:0] = 96, Chop Enabled)
CHANNEL B
CH B CH B CH B CH B CH B
08367-046
1/fADC
Figure 49. Channel Change (Sinc3 Chop Enable)
Rev. A | Page 44 of 56
08367-047
AD7193
The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 52 is achieved. The output data rate is unchanged but the 50 Hz/60 Hz 1 Hz rejection improves to 73 dB typically.
0 -10 -20 -30
The settling time is equal to tSETTLE = 1/fADC Table 33 lists sample FS words and the corresponding output data rates and settling times. Table 33. Examples of Output Data Rates and the Corresponding Settling Time (Fast Settling Mode, Sinc4)
FS[9:0] 96 30 6 5 Average 16 16 16 16 Output Data Rate 2.63 Hz 8.4 Hz 42.1 Hz 50.53 Hz Settling Time 380 ms 118.75 ms 23.75 ms 19.79 ms
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110 0 25 50 75 100 125 150
08367-049
When the analog input channel is changed, there is no additional delay in generating valid conversions--the device functions as a zero latency ADC.
CHANNEL CONVERSIONS
CHANNEL A CH A CH A CH A CHANNEL B
-120
FREQUENCY (Hz)
CH B CH B CH B CH B CH B CH B
08367-051
Figure 52. Sinc3 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
1/fADC
FAST SETTLING MODE (SINC4 FILTER)
In fast settling mode, the settling time is close to the inverse of the first filter notch; therefore, the user can achieve 50 Hz and/or 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. The settling time is equal to 1/output data rate. Therefore, the conversion time is constant when converting on a single channel or when converting on several channels. There is no added latency when switching channels. Enable the fast settling mode using Bit AVG1 and Bit AVG0 in the mode register. In fast settling mode, a postfilter is included after the sinc4 filter. The postfilter averages by 2, 8, or 16, depending on the settings of the AVG1 and AVG0 bits.
ADC
Figure 54. Fast Settling, Sinc4 Filter
When the device is converting on a single channel and a step change occurs on the analog input, the ADC does not detect the change and continues to output conversions. If the step change is synchronized with the conversion, only fully settled results are output from the ADC. However, if the step change is asynchronous to the conversion process, there is one intermediate result, which is not completely settled (see Figure 55).
ANALOG INPUT VALID ADC OUTPUT
08367-052
1/fADC
Figure 55. Step Change on Analog Input, Sinc4 Filter
CHOP MODULATOR SINC3/SINC4 POST FILTER
08367-050
Figure 53. Fast Settling Mode, Sinc4 Filter
The output data rate is the same for chop enabled and chop disabled in fast settling mode. However, when chop is enabled, the settling time equals tSETTLE = 2/fADC Therefore, if chop is enabled, the sinc4 filter is selected, FS[9:0] is set to 6, and averaging by 16 is enabled. The output data rate is equal to 42.1 Hz when the master clock equals 4.92 MHz. Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms and the settling time is equal to 47.5 ms.
Output Data Rate and Settling Time, Sinc4 Filter
With chop disabled, the output data rate is fADC = fCLK/((4 + Avg - 1) x 1024 x FS[9:0]) fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). Avg is the average. FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. If AVG1 = AVG0 = 0, the fast settling mode is not enabled. In this case, Equation 1 is not relevant. (1)
50 Hz/60 Hz Rejection, Sinc4 Filter
Figure 56 shows the frequency response when FS[9:0] is set to 6 and the postfilter averages by 16. This gives an output data rate of 42.10 Hz when the master clock equals 4.92 MHz. The sinc filter places the first notch at fNOTCH = fCLK/(1024 x FS[9:0])
Rev. A | Page 45 of 56
AD7193
The postfiltering places notches at fNOTCH/Avg (Avg is the amount of averaging) and multiples of this frequency; therefore, when FS[9:0] is set to 6 and the postfilter averaging is 16, a notch is placed at 800 Hz due to the sinc filter and notches are placed at 50 Hz and multiples of 50 Hz due to the postfilter. The notch at 50 Hz is a first-order notch; therefore, the notch is not wide. This means that the rejection at 50 Hz exactly is good, assuming a stable 4.92 MHz master clock. However, in a band of 50 Hz 1 Hz, the rejection degrades significantly. The rejection at 50 Hz 0.5 Hz is 40 dB minimum, assuming a stable clock; therefore, a good master clock source is recommended when using fast settling mode.
0 -10 -20 -30
FILTER GAIN (dB)
0 -10 -20 -30
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110
0 30 60 90 120 150
08367-059 08367-157
-120
FREQUENCY (Hz)
Figure 58. Filter Response for Average + Decimate Filter (Sinc4 Filter, FS[9:0] = 30, Average by 16)
-40 -50 -60 -70 -80 -90 -100 -110
0 30 60 90 120 150
08367-053
Simultaneous 50 Hz and 60 Hz rejection is also achieved by using an FS word of 96 and averaging by 16; this places a notch at 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see Figure 59). The output data rate is reduced to 2.63 Hz with this configuration but the rejection is improved to 100 dB typically at 50 Hz 1 Hz and 60 Hz 1 Hz.
0 -10 -20 -30 FILTER GAIN (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 30 60 90 FREQUENCY (Hz) 120
-120
FREQUENCY (Hz)
Figure 56. Filter Response for Average + Decimate Filter (Sinc4 Filter, FS[9:0] = 6, Average by 16)
Figure 57 shows the filter response when FS[9:0] is set to 5 and the postfilter averages by 16. In this case, the output data rate is equal to 50.53 Hz (4.92 MHz master clock) while the first filter notch is placed at 60 Hz. The rejection at 60 Hz 0.5 Hz is equal to 40 dB minimum.
0 -10 -20 -30
150
FILTER GAIN (dB)
-40 -50 -60 -70 -80 -90 -100 -110
0 30 60 90 120 150
08367-058
Figure 59. Filter Response for Average + Decimate Filter (Sinc4 Filter, FS[9:0] = 96, Average by 16)
-120
FREQUENCY (Hz)
Figure 57. Filter Response for Average + Decimate Filter (Sinc4 Filter, FS[9:0] = 5, Average by 16)
Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is set to 30 and the postfilter averages by 16. The output data rate is equal to 8.4 Hz whereas the rejection at 50 Hz 0.5 Hz and 60 Hz 0.5 Hz is 44 dB typically.
Rev. A | Page 46 of 56
AD7193
FAST SETTLING MODE (SINC3 FILTER)
In fast settling mode, the settling time is close to the inverse of the first filter notch. Therefore, the user can achieve 50 Hz and/or 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. The settling time is equal to 1/output data rate. Therefore, the conversion time is constant when converting on a single channel or when converting on several channels. There is no added latency when switching channels. The fast settling mode is enabled using Bit AVG1 and Bit AVG0 in the mode register. A postfilter is included after the sinc4 filter. The postfilter averages by 2, 8, or 16, depending on the settings of the AVG1 and AVG0 bits.
ADC
If the analog input channel is changed, there is no additional delay in generating valid conversions and the device functions as a zero latency ADC.
CHANNEL CONVERSIONS CHANNEL A
CH A CH A CH A
CHANNEL B
CH B CH B CH B CH B CH B
CH B
08367-056
1/fADC
Figure 61. Fast Settling, Sinc3 Filter
CHOP
MODULATOR
SINC3/SINC4
POST FILTER
08367-055
When the device is converting on a single channel and a step change occurs on the analog input, the ADC does not detect the change and continues to output conversions. When the step change is synchronized with the conversion, only fully settled results are output from the ADC. However, if the step change is asynchronous to the conversion process, one intermediate result is not completely settled (see Figure 62).
ANALOG INPUT VALID ADC OUTPUT
08367-057
Figure 60. Fast Settling Mode, Sinc3 Filter
Output Data Rate and Settling Time, Sinc3 Filter
With chop disabled, the output data rate is fADC = fCLK/((3 + Avg - 1) x 1024 x FS[9:0]) fADC is the output data rate. fCLK is master clock (4.92 MHz nominal). Avg is the average. FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. If AVG1 = AVG0 = 0, the fast settling mode is not enabled. In this case, the preceding equation is not relevant. The settling time is equal to tSETTLE = 1/fADC Table 34 lists some sample FS words and the corresponding output data rates and settling times. Table 34. Examples of Output Data Rates and the Corresponding Settling Time (Fast Settling Mode, Sinc3)
FS[9:0] 96 30 6 5 Average 16 16 16 16 Output Data Rate 2.78 Hz 8.9 Hz 44.44 Hz 53.3 Hz Settling Time 360 ms 112.5 ms 22.5 ms 18.75 ms
1/fADC
Figure 62. Step Change on Analog Input, Sinc3 Filter
50 Hz/60 Hz Rejection, Sinc3 Filter
Figure 63 shows the frequency response when FS[9:0] is set to 6 and the postfilter averages by 16. This gives an output data rate of 44.44 Hz when the master clock is 4.92 MHz. The sinc filter places the first notch at fNOTCH = fCLK/(1024 x FS[9:0]) The postfiltering places notches at fNOTCH/Avg (Avg is the amount of averaging) and multiples of this frequency. Therefore, when FS[9:0] is set to 6 and the postfilter averaging is 16, a notch is placed at 800 Hz due to the sinc filter and notches are placed at 50 Hz and multiples of 50 Hz due to the postfilter. The notch at 50 Hz is a first-order notch. Therefore, the notch is not wide. This means that the rejection at 50 Hz exactly is good, assuming a stable 4.92 MHz master clock. However, in a band of 50 Hz 1 Hz, the rejection degrades significantly. The rejection at 50 Hz 0.5 Hz is 40 dB minimum, assuming a stable clock; therefore, a good master clock source is recommended when using fast settling mode.
Rev. A | Page 47 of 56
AD7193
0 -10 -20 -30
FILTER GAIN (dB) FILTER GAIN (dB)
08367-053
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
0 30 60 90 120 150 0 30 60 90 120 150
08367-054 08367-164
-40 -50 -60 -70 -80 -90 -100 -110 -120
-120
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 63. Filter Response for Average + Decimate Filter (Sinc3 Filter, FS[9:0] = 6, Average by 16)
Figure 65. Filter Response for Average + Decimate Filter (Sinc3 Filter, FS[9:0] = 30, Average by 16)
Figure 64 shows the filter response when FS[9:0] is set to 5 and the post filter averages by 16. In this case, the output data rate is equal to 53.33 Hz when the first filter notch is placed at 60 Hz. The rejection at 60 Hz 0.5 Hz is equal to 40 dB minimum.
0 -10 -20 -30
FILTER GAIN (dB)
Simultaneous 50 Hz and 60 Hz rejection is also achieved by using an FS word of 96 and averaging by 16, which places a notch at 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see Figure 66). The output data rate is reduced to 2.78 Hz with this configuration, but the rejection is improved to 94 dB typically at 50 Hz 1 Hz and 60 Hz 1 Hz.
0 -10 -20 -30 FILTER GAIN (dB) -40 -50 -60 -70 -80 -90
-40 -50 -60 -70 -80 -90 -100 -110 0 30 60 90 120 150
08367-058
-120
-100 -110 -120 0 30 60 90 FREQUENCY (Hz) 120
FREQUENCY (Hz)
Figure 64. Filter Response for Average + Decimate Filter (Sinc3 Filter, FS[9:0] = 5, Average by 16)
150
Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is set to 30 and the postfilter averages by 16. The output data rate is equal to 8.9 Hz whereas the rejection at 50 Hz 0.5 Hz and 60 Hz 0.5 Hz is 42 dB typically.
Figure 66. Filter Response for Average + Decimate Filter (Sinc3 Filter, FS[9:0] = 96, Average by 16)
Rev. A | Page 48 of 56
AD7193
FAST SETTLING MODE (CHOP ENABLED)
Chop can be enabled in the fast settling mode. With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins are then inverted, and another settled conversion is obtained. Subsequent conversions are averaged so that the offset is minimized. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. Chopping does not change the output data rate. However, the settling time equals tSETTLE = 2/fADC Consequently, if chop is enabled, the sinc4 filter is selected, FS[9:0] is set to 6 and averaging by 16 is enabled, and the output data rate is equal to 42.1 Hz. Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms and the settling time is equal to 47.5 ms.
Rev. A | Page 49 of 56
AD7193
SUMMARY OF FILTER OPTIONS
The AD7193 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, and the 50 Hz/60 Hz rejection. Table 35. Filter Summary 1
Filter Sinc4, Chop Disabled 4 Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled, Zero Latency Sinc4, Chop Disabled, Zero Latency Sinc4, Chop Disabled, Zero Latency Sinc4, Chop Enabled Sinc3, Chop Enabled Fast Settling (Sinc4, Chop Disabled, Average by 16) Fast Settling (Sinc4, Chop Disabled, Average by 16) Fast Settling (Sinc4, Chop Disabled, Average by 16) Fast Settling (Sinc3, Chop Disabled, Average by 16) Fast Settling (Sinc4, Chop Disabled, Average by 16) Fast Settling (Sinc3, Chop Disabled, Average by 16)
1 2
Table 35 shows some sample configurations and the corresponding performance in terms of throughput, settling time, and 50 Hz/60 Hz rejection.
FS[9:0] 1 5 5 480 480 96 96 96 96 80 80 96 96 80 96 96 96 96 5 5 6 6
Output Data Rate (Hz) 4800 960 960 10 10 50 50 50 50 60 60 12.5 12.5 15 12.5 16.7 2.63 2.78 50.53 53.33 42.10 44.44
Settling Time (ms) 0.83 4.17 3.125 400 300 80 80 60 60 66.67 50 80 80 66.67 160 120 380 360 19.79 18.75 23.75 22.5
Throughput 2 (Hz) 1200 240 320 2.5 3.33 12.5 12.5 16.7 16.7 15 20 12.5 12.5 15 6.25 8.33 2.63 2.78 50.53 53.33 42.1 44.44
REJ60 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 0 0 0 0
50 Hz Rejection (dB) 3 No 50 Hz or 60 Hz rejection No 50 Hz or 60 Hz rejection No 50 Hz or 60 Hz rejection 120 dB (50 Hz and 60 Hz) 100 dB (50 Hz and 60 Hz) 120 dB (50 Hz only) 82 dB (50 Hz and 60 Hz) 95 dB (50 Hz only) 67 dB (50 Hz and 60 Hz) 120 dB (60 Hz only) 95 dB (60 Hz only) 120 dB (50 Hz only) 82 dB (50 Hz and 60 Hz) 120 dB (60 Hz only) 80 dB (50 Hz and 60 Hz) 67 dB (50 Hz and 60 Hz) 100 dB (50 Hz and 60 Hz) 94 dB (50 Hz and 60 Hz) 40 dB (60 Hz only) 40 dB (60 Hz only) 40 dB (50 Hz only) 40 dB (50 Hz only)
These calculations assume a 4.92 MHz stable master clock. Throughput is the rate at which conversions are available when several channels are enabled. In zero latency mode, the output data rate and throughput are equal. 3 For fast settling mode, the 50 Hz/60 Hz rejection is measured in a band of 0.5 Hz around 50 Hz and/or 60 Hz. For all other modes, a region of 1 Hz around 50 Hz and/or 60 Hz is used. 4 For output dates rates greater than 1 kHz, the sinc4 filter is recommended.
Rev. A | Page 50 of 56
AD7193 GROUNDING AND LAYOUT
Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7193 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. Connect an R-C filter to each analog input pin to provide rejection at the modulator sampling frequency. A 100 resistor in series with each analog input, a 0.1 F capacitor between the analog input pins, and a 0.01 F capacitor from each analog input to AGND are advised. The digital filter also removes noise from the analog and reference inputs provided that these noise sources do not saturate the analog modulator. As a result, the AD7193 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7193 is so high and the noise levels from the converter so low, care must be taken with regard to grounding and layout. The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Although the AD7193 has separate pins for analog and digital ground, the AGND and DGND pins are tied together internally via the substrate. Therefore, the user must not tie these two pins to separate ground planes unless the ground planes are connected together near the AD7193. In systems in which the AGND and DGND are connected somewhere else in the system (that is, the power supply of the system), they should not be connected again at the AD7193 because a ground loop results. In these situations, it is recommended that the ground pins of the AD7193 be tied to the AGND plane. In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND. Avoid running digital lines under the device because this couples noise onto the die, and allows the analog ground plane to run under the AD7193 to prevent noise coupling. The power supply lines to the AD7193 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. Decouple all analog supplies with 10 F tantalum capacitors in parallel with 0.1 F capacitors to AGND. To achieve the best results from these decoupling components, place them as close as possible to the device, ideally right up against the device. Decouple all logic chips with 0.1 F ceramic capacitors to DGND. In systems in which a common supply voltage is used to drive both the AVDD and DVDD of the AD7193, it is recommended that the system AVDD supply be used. For this supply, place the recommended analog supply decoupling capacitors between the AVDD pin of the AD7193 and AGND and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7193 and DGND.
Rev. A | Page 51 of 56
AD7193 APPLICATIONS INFORMATION
The AD7193 provides a low cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a - architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. placed in power-down mode, thus significantly reducing the power consumed in the application. In addition, the bridge power-down switch can be opened while the AD7193 is in powerdown mode, thus avoiding unnecessary power consumption by the front-end transducers. When the parts are taken out of power-down mode and the bridge power-down switch is closed, the user should ensure that the front-end circuitry is fully settled before attempting a read from the AD7193. In Figure 67, temperature compensation is performed using a thermistor. In addition, the reference voltage for the temperature measurement is derived from a precision resistor in series with the thermistor. This allows a ratiometric measurement so that variation of the excitation voltage has no affect on the measurement (it is the ratio of the precision reference resistance to the thermistor resistance that is measured) For simplicity, external filters are not shown in Figure 67; however, an R-C antialias filter must be included on each analog input. This is required because the on-chip digital filter does not provide any rejection around the modulator sampling frequency or multiples of this frequency. Suitable values are a 100 resistor in series with each analog input, a 0.1 F capacitor between the analog input pins, and a 0.01 F capacitor from each analog input pin to AGND.
FLOWMETER
Figure 67 shows the AD7193 being used in a flowmeter application that consists of two pressure transducers with the rate of flow being equal to the pressure difference. The pressure transducers are arranged in a bridge network and give a differential output voltage between its OUT+ and OUT- terminals. With rated full-scale pressure (in this case 300 mmHg) on the transducer, the differential output voltage is 3 mV/V of the input voltage (that is, the voltage between the IN+ and IN- terminals). Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The excitation voltage for the bridge can be used to directly provide the reference for the ADC, because the reference input range includes the supply voltage. A second advantage of using the AD7193 in transducer based applications is that the bridge power-down switch can be fully utilized in low power applications. The bridge power-down switch is connected in series with the cold side of the bridges. In normal operation, the switch is closed and measurements are taken. In applications where power is of concern, the AD7193 can be
5V
IN+ OUT- IN+ OUT- OUT+ IN- OUT+
REFIN1(+) AGND AIN1 AIN2
AVDD AVDD
DVDD DGND
REFERENCE DETECT
IN-
AIN3 AIN4 AIN5 AIN6
MUX
PGA
- ADC
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY DIN SCLK CS SYNC
AGND REFIN2(+) REFIN2(-) REFIN1(-) BPDSW AGND MCLK1 MCLK2
AD7193
CLOCK CIRCUITRY
08367-064
Figure 67. Typical Application (Flowmeter)
Rev. A | Page 52 of 56
AD7193 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 68. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7193BRUZ 1 AD7193BRUZ-REEL1
1
Temperature Range -40C to +105C -40C to +105C
Package Description 28-Lead TSSOP 28-Lead TSSOP
Package Option RU-28 RU-28
Z = RoHS Compliant Part.
Rev. A | Page 53 of 56
AD7193 NOTES
Rev. A | Page 54 of 56
AD7193 NOTES
Rev. A | Page 55 of 56
AD7193 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08367-0-9/09(A)
Rev. A | Page 56 of 56

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